Programmable logic devices such as field programmable gate arrays (FPGAs) are typically configured by a user using a configuration bitstream that is stored in a configuration memory. This configuration memory may be either a non-volatile memory such as FLASH or a volatile memory such as SRAM. For a variety of reasons such as speed, SRAM-based FPGAs currently dominate the programmable logic device market. However, FPGAs have been developed which include embedded SRAM and FLASH memories. Such FPGAs enjoy the speed advantage of SRAM yet retain their configuaion upon power-down. Thus, the incorporation of embedded FLASH memories into FPGAs is a growing trend.
The integration of FLASH memory into a programmable logic device introduces a number of complications. Programming or erasing FLASH involves the use of relatively large voltages that would destroy the logic core of a programmable logic device such as an FPGA. Various adaptations have been developed to facilitate the handling of the relatively large voltages within FLASH memories. In particular, FLASH memories are commonly formed using a “triple p well” construction. A triple p-well 100 is illustrated in FIG. 1. During erasure of a FLASH memory cell, relatively large negative voltages such as −10 V may be transmitted through transistors such as an NMOS transistor 105. Should an n+ doped source of transistor 105 be brought that low on a grounded p-type substrate, a forward-biased p-n junction would result such that the source would clamp at approximately −0.7 V. To allow normal transistor operation in the presence of such a large negative voltage, transistor 105 is formed in an inner p-well 110 that in turn is formed in an n-well 115 formed in a p-type substrate 120. In this fashion, inner p-well 110 may be brought negative through a p-well bias applied to a p+ doped contact 125. For example, if negative 10 V is applied to the drain of the NMOS transistor, −10 V may also be applied to contact 125. Because n-well 115 may be grounded through an N-well bias at an n+ doped contact 130, no forward-biased p-n junctions result. Thus, the −10 V potential may flow through transistor 105 in a normal fashion. The term “triple” well arises because the substrate may be considered a first well, then n-well a second well, and the inner p-well a third well.
Although the use of a triple p-well allows the propagation of negative voltages in FLASH memories and other applications, the triple p well demands considerable die space. Accordingly, there is a need in the art for denser memories that accommodate negative voltages.